Phase locked loops (PLLs) are widely used in a variety of electronic applications and circuits including, but not limited to, telecommunications, computers, clock and data recovery circuits, frequency synthesizers, and analog-to-digital converts. PLLs may be implemented using analog components, digital components, and combinations thereof. Analog PLLs occupy large circuit areas, are susceptible to process, voltage and temperature variations, and have substantial power requirements as compared to digital PLLs. Digital PLLs, however, also suffer from certain disadvantages. For example, large loop gain factors are needed to guarantee loop stability and achieve high bandwidths in the digital PLL. Large loop gain factors, however, translate into high quantization noise and high jitter performance.
A technique for improving the performance of the digital PLLs is to use time to digital converters (TDC) as the phase detector. There are multiple drawbacks with using TDCs in digital PLLs. TDCs are very expensive in terms of power and area and performance of the PLL is limited by the resolution of the TDC. In addition, implementing the TDC in the digital PLL is complex. To achieve performance similar to analog PLLs, tens of femtoseconds of accuracy is required, which is very hard to achieve in advanced complementary metal-oxide-semiconductor (CMOS) technologies.